The present invention relates to a liquid crystal display and a method of manufacturing the same and, in particular, relates to an in-plane switching (IPS) liquid crystal display in which signal lines are partially covered with a common electrode via an interlayer insulating film.
Conventionally, use has been widely made of transmission type liquid crystal displays employing thin film transistors (TFTs) or metal-insulator-metal (MIM) devices as switching elements for driving and controlling pixel electrodes. Particularly, IPS liquid crystal displays have been used as monitors, which can realize wide viewing angles like cathode ray tubes (CRTs).
FIGS. 1 to 3 show structures of a one-pixel portion of an active matrix substrate in a conventional IPS liquid crystal display using TFTs disclosed in WO98/47044 (pp. 8 –18, FIGS. 1, 3 and 4, it will be hereinafter referred to as a conventional reference). Herein, FIG. 1 is a plan view, FIG. 2 is a sectional view taken along line X–X′ in FIG. 1, and FIG. 3 is a sectional view taken along line Y–Y′ in FIG. 1. In the active matrix substrate of the IPS liquid crystal display, a plurality of pixel electrodes and a common electrode are formed so as to face each other like alternate teeth of opposed combs, and electric fields substantially parallel to the substrate are generated between the electrodes to thereby control orientation of liquid crystal molecules.
As shown in FIG. 1, in the one-pixel portion of the active matrix substrate, a scan line 111 for supplying a scan signal and a signal line 112 for supplying a display signal cross each other at right angles, and common wiring 113 for applying electric potential to a common electrode 122 is arranged in parallel to the scan line 111. On the other hand, the common electrode 122 and a pixel electrode 121 are placed so as to face each other like alternate teeth of opposed combs. In a region defined by crossing between the scan line 111 and the signal line 112, a TFT 114 is provided so as to be connected to the scan line 111, the signal line 112, and the pixel electrode 121.
A gate electrode 123 of the TFT 114 is provided as a part of the scan line 111, a drain electrode 125 is connected to the signal line 112, a source electrode 124 is connected to the pixel electrode 121 via a contact hole 126, and the common wiring 113 is connected to the common electrode 122 via a contact hole 127. Further, the signal line 112 is disposed so as to be partially covered with the common electrode 122.
As shown in FIG. 2, the gate electrode 123, a gate insulating film 131, and an insular semiconductor layer 134 are provided on a transparent insulating substrate 120. Further, the source electrode 124 and the drain electrode 125 are separately provided and cover the semiconductor layer 134 (an amorphous silicon (a-Si) layer 164 and an n+ type amorphous silicon (n+ type a-Si) layer 174), thereby forming the TFT 114. In addition, an interlayer insulating film (a protective film 132 and an organic insulating film 133) is provided so as to cover the TFT 114. Further, as shown in FIG. 3, the pixel electrode 121 is connected to the source electrode 124 via the contact hole 126 formed in the organic insulating film 133 while the common electrode 122 is connected to the common wiring 113 via the contact hole 127 formed in the organic insulating film 133 and the gate insulating film 131.
Now, description will be made of a method of the manufacturing the active matrix substrate having the foregoing structure. First, a metal film made of a Cr—Mo alloy is deposited on the transparent insulating substrate 120 made of glass or the like, then patterning is carried out so as to form the gate electrodes 123, the scan lines 111, and the common wiring 113. Subsequently, after the gate insulating film 131, the a-Si layer 164, and the n+ type a-Si layer 174 are sequentially formed, patterning is performed so as to form the semiconductor layers 134. Thereafter, a metal film made of a Cr—Mo alloy is deposited, and the source electrodes 124, the drain electrodes 125 and the signal lines 112 are formed by patterning. Then, using them as masks, the n+ type a-Si layers 174 are removed by etching to thereby form channels.
Subsequently, the protective film 132 made of silicon nitride is deposited and patterned. Then, the photosensitive organic insulating film 133 is applied and patterned, then using it as a mask, the gate insulating film 131 is patterned to form the contact holes 126 and 127. Thereafter, a transparent conductive film made of indium tin oxide (ITO) is deposited so as to cover the organic insulating film 133, and the common electrode 122 and the pixel electrodes 121 are formed by patterning. In this manner, the connection between the common electrode 122 and the common wiring 113 and the connection between the pixel electrodes 121 and the source electrodes 124 are established.
As described above, the organic insulating film 133 having a low dielectric constant is used as a part of the interlayer insulating film. This is because capacitive coupling between the signal line 112 and the common electrode 122 is reduced and crosstalk is suppressed when the common electrode and the signal line are partially overlapped with each other in order to improve the aperture ratio. Further, the flatness of the active matrix substrate is improved to reduce fluctuation of gaps relative to an opposing substrate, thereby improving uniformity of luminance.
When the organic insulating film is not used in the interlayer insulating film, the protective layer 132 made of silicon nitride is alternatively formed thicker. In this case, the contact holes 126 and 127 are formed through one photolithography process.
In the foregoing IPS liquid crystal display in which the signal lines are partially covered with the common electrode via the interlayer insulating film, however, when pinholes are generated in the interlayer insulating film, the signal lines and the common electrode tend to be short-circuited together to cause a longitudinal line defect. This causes a problem in terms of manufacturing yield
According to experiments by the present inventors, it has been confirmed that, in the patterning process of the signal lines 112, patterning failure of the metal film for the signal lines 112 occurs in regions from the signal lines 112 to the contact holes 127 due to foreign matter such as a photoresist so that the signal lines 112 and the common electrode 112 are short-circuited together via the contact holes 127. It has been found that this phenomenon becomes remarkable particularly in high resolution panels with narrow pixel pitches.
Further, when the interlayer insulating film is formed only by the inorganic film such as the silicon nitride film, i.e. without using the organic insulating film, it has been confirmed that if the contact holes 126 and 127 are formed by the use of at least dry etching, plasma is concentrated on foreign matter or defect portions of a photoresist, so that the interlayer insulating film is resultantly etched to have pinholes, and the signal lines 112 and the common electrode 122 are short-circuited together via the pinholes.